With recent improvements in performances of electronic devices, some semiconductor devices such as LSI in each of which a plurality of types of MOS transistors different in electrical characteristics such as an operation voltage and an operation speed are mixedly mounted on a single semiconductor substrate.
Each MOS transistor includes various impurity regions. Examples of such impurity regions include a channel region, a source drain region, an extension region, a pocket region, and the like.
Among them, the channel region is provided to adjust a threshold voltage of the MOS transistor, and is provided in a portion of the semiconductor substrate between the source drain regions.
Moreover, the extension region is provided to prevent concentration of a high electric field between the source drain region and the channel region. The extension region is formed to be shallower and to have a lower impurity concentration than the source drain regions.
The pocket region is provided to prevent a short channel effect between the source drain regions. The pocket region is formed in a portion of the semiconductor substrate under a gate electrode by implanting an impurity with a conductivity type opposite to that of the source drain regions.
These impurity regions are formed individually by implanting ions of impurities into the semiconductor substrate. However, a product in which a plurality of types of MOS transistors are mixedly mounted as described above needs an increased number of ion implantation steps, which thereby leads to increase in manufacturing cost.
Note that, techniques related to this application are disclosed in International Publication Pamphlet No. WO 2004/112139, Japanese Laid-open Patent Publications Nos. 02-022862 and 2000-77541.